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Josep Torrellas
Results: 154

#	Item
61	Positional Adaptation of Processors: Application to Energy Reduction ∗ Michael C. Huang Jose Renau and Josep Torrellas Dept. of Electrical and Computer Engineering Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-04-01 22:17:30 Subroutines Cache Holism Source code University of Cambridge Computer Laboratory Call stack CPU cache Parameter Algorithm Software engineering Computing Computer programming
62	RelaxReplay: Record and Replay for Relaxed-Consistency Multiprocessors Nima Honarmand and Josep Torrellas University of Illinois at Urbana-Champaign {honarma1,torrella}@illinois.edu http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-01-10 19:23:01 Computing Parallel computing Instruction set CPU cache Microarchitecture Processor register Linearizability MIMD Computer architecture Computer hardware Central processing unit
63	Prototyping Architectural Support for Program Rollback Using FPGAs ∗ Radu Teodorescu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {teodores,torrellas}@cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-05-11 13:27:29 Computer engineering CPU cache Microarchitecture Speculative execution Processor register Application checkpointing Parallel computing Instruction set Multithreading Computer architecture Computer hardware Central processing unit
64	USING AN ADAPTIVE HPC RUNTIME SYSTEM TO RECONFIGURE THE CACHE HIERARCHY SC’14, Nov. 20, 2014 Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-12-19 19:14:48 Central processing unit Ø Slashed zero Numbers Information Computer memory Cache CPU cache
65	An Updated Evaluation of ReCycle Abhishek Tiwari and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu {atiwari,torrellas}@cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:09:56 ReCycle Feedback Reason Microarchitecture Pipeline Recycling Computer architecture Computer hardware Electronic engineering
66	FlexBulk: Intelligently Forming Atomic Blocks in Blocked-Execution Multiprocessors to Minimize Squashes Rishi Agarwal and Josep Torrellas University of Illinois at Urbana-Champaign, USA {agarwa29,torrella}@illinois.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2011-04-01 11:23:57 Parallel computing Lock Compiler optimization C dynamic memory allocation Memory barrier Hazard Critical section Linearizability Concurrency control Computing Computer architecture
67	BulkCommit: Scalable and Fast Commit of Atomic Blocks ∗ in a Lazy Multiprocessor Environment † Xuehai Qian , Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-10-25 19:56:50 Computer file formats Graphics file formats Cache coherency Chunk CPU cache MESI protocol ANIM Parallel computing C dynamic memory allocation Computing Computer memory Computer hardware
68	DeAliaser: Alias Speculation Using Atomic Region Support Wonsun Ahn Yuelu Duan Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-01-25 16:44:16 Software engineering Programming language implementation Central processing unit Computer memory Compiler construction Alias analysis CPU cache Loop unwinding Linearizability Computing Computer architecture Compiler optimizations

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